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-fpga-pld-

基于FPGA设计的一个PID控制系统，完成对物体检测和运动控制；直流电机和步进电机驱动模块是可选的。

00_image_rotate

视频旋转（2019FPGA大赛）

16-qam-qpsk-bpsk

Simulation in MATLAB of Digital Communication modulations (BPSK,QPSK,16 QAM) to find the performance and probability of error in Rayleigh and Rician fading environments

20180225swiftopen

swift包管理

2fsk-2psk-2dpsk-qpsk-code-and-decode

用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调

3-phase-spwm-fpga-

4096bit-iddmm-verilog

4096bit Iterative digit-digit Montgomery Multiplication in Verilog

4in1-modulator-in-verilog

Verilog implementation of a Four(QPSK, BPSK, ASK, FSK) in one Modulator

abc_top

多功能示波器+信号发送器

accelerating_standard_and_modified_aes128

Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms

acoustic_precoding

重要

acousticmfsk

Acoustic MFSK Communication

ad6646_dotrx

adc 6646 for dotrx

ad9361_trx

General purpose FMCOMMS3/ZedBoard based transceiver.

ad9361_tx_1mhz_baseband_800hz_if

A project demonstrate how to config ad9361 to TX mode

ad9361_tx_gmsk

A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK

ad9361_tx_msk

A project demonstrate how to config ad9361 to TX mode and how to transmit MSK

ad9361test

ad936x_lvds_if

ad936x lvds interface

ad936x_lvds_if-1-

ad9957

adalm-pluto

64QAM Wireless communication on ADALM-PLUTO (a SDR active learning module), written in MATLAB, based on some APIs and existing functions.

adc-lvds

Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS

adc_spi_to_axism

Convert from serial data in to an AXI-4 Stream master data source

adi_adrv9371_zc706

adi's adrv9371 example integration with DVB-S2 IP

adrv9009-receiver-signal-path-fir-filter

An attempt to implement the signal path on the receiver side of the ADRV9009, a highly integrated, radio frequency (RF) transceiver.

aes-128

RTL implementation of the AES algorithm with 128-bit key using Verilog.

aes-based-on-fpga

AES-based-on-FPGA developed by verilog.

am

AM调制解调的FPGA实现

antsdr-fw_-

ANTSDR Firmware