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4-port-gigabit-ethernet-switch

Project in course “FPGA Design for Communication Systems”

alchitry-litex

litex examples for the Alchitry FPGA boards

arty_ntp_client

NTP client for Arty-7 35T board

au-bridge

Bridge configuration to allow programming of the flash chip over JTAG on the Alchitry Au

axi-display-controller

axi-register-bank

AXI Register Bank IP-Core

axi2spi-bridge

Homework for Rendszerarchitekturak with Feher Béla & Wacha Gabor :)

axi4-interface

AXI4 and AXI4-Lite interface definitions

axi4litetosimpleconverter

This module converts AXI4 Lite to simple interface

axi_lite

AXI Lite module RTL

axi_lite-and-axi-full-test

axi_sitcp

SiTCP wrapper

axis_to_uart

IP-ядро преобразующее AXI-Stream в UART и обратно

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

cute-a7-wrf

cute a7 example design

cw310-bergen-board

CW310 - Kintex FPGA ('Bergen Board') Target

daisho

Test of the USB3 IP Core from Daisho on a Xilinx device

ddr-ram-controller-mig

DDR SDRAM Controller based on Xilinx MIG for Digilent Boards

dds-ip

A simple waveform generator using Direct Digital Synthesis, working as an AXI Lite IP

designing-a-custom-axi-slave-peripheral

A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools

dram-arty-a7

dvp_to_udp

Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA

dyna-kinematics

A 2D rigid-body dynamics simulator with some cool features for generating beautiful animations.

ebaz4205_88e1512_sfp

EBAZ4205_88E1512_SFP 千兆以太网+SFP+VGA+W8960

ed_lib

Implementations of edge (ED, EDColor, EDPF), line (EDLines), circle and low eccentric ellipse (EDCircles) detection algorithms.

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

esg_hdl

Convenient FPGA communication

eth_vlg

ethernet-design-verilog

Gigabit Ethernet UDP communication driver

ethernet-fmc-zynq-gem

Example design for the Ethernet FMC using the hard GEMs of the Zynq