Comments (5)
lanza
commented on May 25, 2024
2
Yea, I'll add this to my todo list to get a port to llvm-17 release. Hopefully this week!
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lanza
commented on May 25, 2024
1
https://github.com/llvm/clangir/tree/clangir-17 done!
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bcardosolopes
commented on May 25, 2024
@lanza do you have the bandwidth to pull this up at some point? The sycl-clangir branch probably contains most of the necessary work, though it's possible that you had to work on some bigger changes post July.
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xlauko
commented on May 25, 2024
If it's too complex I can survive with the current state for now, but keep it in mind for next 18 release.
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bcardosolopes
commented on May 25, 2024
Thanks Nathan!
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Related Issues (20)
- Remove redundant bitcast in builtin dynamic alloca codegen
- Unable to compile due to missing "MakeNaturalAddressForPointer" in CIRGenFunction HOT 1
- Global "NaN" Is Lowered to `0.0` During LLVM Conversion HOT 9
- Through MLIR lowering (not LLVM): Missing CIR operations HOT 11
- Can I try to make a lowering operation for cir.cos? HOT 1
- Vtable support for simple multiple inheritance without thunk HOT 2
- Prevent eye bleeding type repetition in the assembly form of ConstantOp. HOT 5
- Add CIRGen and LowerToLLVM support for remaining pointer arithmetic extensions for C HOT 2
- Change ops to be consistent in their MLIR ASM style HOT 3
- Miss destruction in switch statements HOT 4
- Module verification error of switch statements HOT 3
- AArch64 specific builtins/intrinsics
- Debug info support
- Move more logic from MergeCleanups into Op::fold methods HOT 2
- Add switch support for GNU range HOT 1
- Use the canonicalizer pass for the new operations in CIR (with workaround sharing) HOT 2
- Enhance the extensibility of TargetCIRGenInfo to support more targets HOT 1
- Incorrect terminator generation HOT 3
- Fix InitListExpr for OpenCL vectors HOT 4
- [Documentation] Encode rules for skeleton, asserts, unrecheable, testing, etc HOT 1
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