Comments (1)
The CIR looks like
!s32i = !cir.int<s, 32>
#fn_attr = #cir<extra({inline = #cir.inline<no>, optnone = #cir.optnone})>
#loc3 = loc("<stdin>":1:11)
#loc4 = loc("<stdin>":1:15)
#loc7 = loc(fused[#loc3, #loc4])
module attributes {cir.lang = #cir.lang<cxx>, cir.sob = #cir.signed_overflow_behavior<undefined>, dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<!llvm.ptr<270>, dense<32> : vector<4xi64>>, #dlti.dl_entry<!llvm.ptr<271>, dense<32> : vector<4xi64>>, #dlti.dl_entry<f128, dense<128> : vector<2xi64>>, #dlti.dl_entry<f16, dense<16> : vector<2xi64>>, #dlti.dl_entry<f64, dense<64> : vector<2xi64>>, #dlti.dl_entry<i64, dense<64> : vector<2xi64>>, #dlti.dl_entry<i128, dense<128> : vector<2xi64>>, #dlti.dl_entry<!llvm.ptr<272>, dense<64> : vector<4xi64>>, #dlti.dl_entry<!llvm.ptr, dense<64> : vector<4xi64>>, #dlti.dl_entry<f80, dense<128> : vector<2xi64>>, #dlti.dl_entry<i16, dense<16> : vector<2xi64>>, #dlti.dl_entry<i32, dense<32> : vector<2xi64>>, #dlti.dl_entry<i1, dense<8> : vector<2xi64>>, #dlti.dl_entry<i8, dense<8> : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"} {
cir.func @_Z4testPi(%arg0: !cir.ptr<!s32i> loc(fused[#loc3, #loc4])) extra(#fn_attr) {
%0 = cir.alloca !cir.ptr<!s32i>, !cir.ptr<!cir.ptr<!s32i>>, ["", init] {alignment = 8 : i64} loc(#loc7)
cir.store %arg0, %0 : !cir.ptr<!s32i>, !cir.ptr<!cir.ptr<!s32i>> loc(#loc5)
cir.return loc(#loc2)
} loc(#loc6)
} loc(#loc)
#loc = loc(unknown)
#loc1 = loc("<stdin>":1:1)
#loc2 = loc("<stdin>":1:18)
#loc5 = loc("<stdin>":1:17)
#loc6 = loc(fused[#loc1, #loc2])
from clangir.
Related Issues (20)
- Should use `getCalleeAttr` when lowering `CallOp`
- Should mark private visibility for extern symbols.
- Vector related arith missing `nsw` on addition HOT 2
- Revisit insertion point being restored by an InsertionGuard in `buildSwitchBody()` HOT 1
- [Umbrella] Switch stmt CIRGen issues
- Single-operand vector shuffling HOT 1
- [ThroughMLIR] cir-opt can not work when lowering ForOp to scf HOT 4
- Add a test for arrays of 3-component extended vectors
- Crash with try statement HOT 1
- [GSoC] Add OpenCL support to compile GPU kernels
- Reinstate #668 and #678 HOT 2
- Verify ZdlPv -> ZdlPvm in `test/CIR/CodeGen/dtors.cpp`
- Verify gep uses moving to i64
- Replace uses of `isa`/`dyn_cast`/`cast`/... member functions HOT 2
- Data layout modeling for CIR types
- Add support for `__atomic_thread_fence` HOT 3
- Add canonicalization passes for cir.complex.create
- Problem with emitting MLIR from CIR: `cir.func` gets `dsolocal` attribute HOT 4
- Non-constant memory order in atomic built-ins HOT 3
- Keep higher level abstraction for runtime memory orders on atomics
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from clangir.