Comments (1)
The FIFO will not be overflowed if you write the packet size + 64 bytes of data. Actually the FIFO size is 65 bytes wide when variable length is used and it is 66 bytes wide in case of variable length and an address byte is used.
Yes, you are right the usage of RxBuffer variable is not correct. A correction will be provided in a future release.
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Related Issues (20)
- How to get the frequency on OnRxData
- TX Timeout hardcoded HOT 1
- DL not received in Class C AS923-1 + Freq 923.600
- Pre-certification should always failed due to duty-cycle limitation HOT 2
- Stack writes to NVM while radio is transmitting
- TimerInit called multiple times on the same TimerEvent_t struct HOT 1
- Race condition in RtcGetCalendarValue on NucleoL476 board
- LORAMAC_TX_CONFIG tested, but never set.
- GpioMcuRemoveInterrupt sets GPIO pull-up/pull-down registers to random uninitialized memory
- Secure-Element Preprocessor definition ifndef wrapping HOT 1
- AES function rename due to multiple definitions linking error
- LmHandlerInit causing some current leakage till the first tx HOT 3
- The correct value of MinRxSymbols? HOT 1
- does any body port this project for stm32f103?
- Does the Firmware Management (Port 203) is supported by LoRaMac-Node ? HOT 2
- Errata 2.3 current implementation may impact TX configuration
- MacBook M1 chip complies fail! arm-none-eabi-gcc: error: unrecognized command-line option '-arch'; did you mean '-march='?
- Support for MSPM0 Microcontroller
- stm32系列的Unique Devices IDs register错误
- Radio.Sleep() may leave antenna switch powered HOT 1
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