Related Issues (20)
- A bit-flip in the ECC-protected register file can go unnoticed when writeback forwarding is enabled
- ebreak mtval HOT 2
- Illegal_reg_rv32e not updated on two consecutive multicycle invalid instructions HOT 1
- Pipeline not being flushed on PMP register clears HOT 1
- Integration of 6T SRAM with the Ibex core HOT 5
- ibex build break on older verilator version HOT 3
- How to connect the SRAM generated by the memory compiler to the Ibex core and verify its functionality? HOT 5
- Tests failing when running regression using Questa
- Ibex simple system cannot simulate with timing flag in Verilator HOT 2
- [doc] Disambiguate doc around ECC detection on the data interface HOT 2
- [rtl] Implement Zbkb - scalar crypto bitmanip
- [rtl] Declare Zkt - Scalar crypto data independent execution latency compliance
- Problem with ibex_alu.sv when synthesis with genus cadence HOT 1
- Compile_tb.py generate options not recogised by xrun HOT 13
- Why did you use kGE to estimate area and not the usual units of measurement?
- Why did you use kGE to estimate area and not the usual units of measurement HOT 2
- error gen wrong path and failed to create spike-cosim_trace_core.log file by xrun HOT 1
- Missing `ifdef guard from assertion in ibex_core.sv HOT 5
- regfile_latch: oh_raddr_a_err signal generated based on raddr_b_int HOT 4
- [rtl] Refactor register files to bring common logic together
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