Related Issues (20)
- Is it possible to support Verilator as the RTL simulator for cosim?
- x0 is not zero HOT 1
- Trap Return with activated Branch Prediction results in an unintended instruction retire
- Report a bug in Ibex
- Spike not generating csrrw and compressed instructions
- Incorrect stalling behaviour for configurations with writeback stage but without branch target ALU results in an incorrect branch target HOT 1
- Ask a question related to Ibex
- [dv] Implement fault injection test for hardening in register file HOT 1
- [dv] Implement spurious memory response test HOT 2
- Store instructions do not always raise RV32E exceptions HOT 3
- Objcopy as replacement to srec_cat command
- `ecall` are counted as faults for `double_fault_seen_o` HOT 5
- [rtl] Behaviour of debug single stepping with dummy instruction insertion may be surprising HOT 3
- [dv] Deep dive regression triage HOT 2
- A bit-flip in the ECC-protected register file can go unnoticed when writeback forwarding is enabled
- ebreak mtval HOT 2
- Illegal_reg_rv32e not updated on two consecutive multicycle invalid instructions HOT 1
- Pipeline not being flushed on PMP register clears
- Integration of 6T SRAM with the Ibex core
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