Brainstorm required features for clive

[marthinwurer]

Brainstorm required features for clive

[marthinwurer]

Start interpreted, then move to code generation in other languages. Do really dumb code generation first, work on non-constant optimizations later.
Definite targets:
x86
C
VHDL
Verilog

Start with pure functional, add other features later.

Strong optional typing - will need to convert types. (Is it possible to do polymorphism by return type too? probably.)
Can duck typing be mixed in? Would have to trace where object is used and make sure that it supports all required types for function calls and dereferences.

Use @ for annotations (need to figure out how those work)

Base types:
True
False
array (Maybe vector/list/resizable type too?)
Enum

Can try to build all other types out of these, but should probably make some generic ones.
need a typedef for generics.

Oh yeah, generics. hopefully no template metaprogramming here

Want effectively vhdl entities (in, bus, out) - these are basically interfaces for state.
Functions
types(basically objects, also want properties)
probably no statics?
Types, functions, and entities can have different implementations. These need to be selected in some way, and the default implementation should be able to be overridden at runtime.
Implementation of

Modules would be nice.
x.y.module is standard for a lot of languages; I don't know why I'd change it unless things were confusing.