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ao486

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

black-parrot-branch-predictor

Branch Predictor Optimization for BlackParrot

caravel_fpu

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-training

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cores-swerv

SweRV EH1 core

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

imperas-riscv-tests

lm-riscv-dv

An Open-Source Design and Verification Environment for RISC-V

openc910

OpenXuantie - OpenC910 Core

quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

riscv-arch-test

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-soc-book

关于RISC-V你所需要知道的一切

rocket-chip

Rocket Chip Generator

verilog_test

just for test!

vroom

VRoom! RISC-V CPU

xiangshan

Open-source high-performance RISC-V processor

xs-verilog-library