mcjtag Goto Github PK
Name: Dmitry Matyunin
Type: User
Dmitry Matyunin's Projects
axis-uart
AXI Stream UART (verilog)
axis_usbd
AXI-Stream USB 2.0 HS Device Bridge (Verilog)
bitonic_sorter
Bitonic sorter (Batcher's sorting network) written in Verilog.
cyclic_code
Cyclic code over GF(2) - Verilog
dw_fifo
Asymmetrical FIFO with dynamic width
eth_switch
Verilog Ethernet Switch (layer 2)
eval-kits
Milandr Evaluation Kits
fpga_basic
FPGA basic digital devices
fpga_dsp
DSP in FPGA
hamming_code
Hamming code implementation in Verilog
hash_table
Hash Table on Verilog
mdma
AXI Mini Direct Memory Access (verilog)
msnr
Signal-to-Noise Calculation (written in Matlab scripting language)
poly_arithmetic
Polynomial arithmetic (Verilog)
rvs-dft
Real-Valued Sequences DFT algorithms
tcam
TCAM (Ternary Content-Addressable Memory) in Verilog
v8b10b
Verilog 8b10b encoder/decoder
vgac
Dynamic VGA Controller
z7cat
Zynq-7000 MCS Creator
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