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MicroDynamics CPU's Projects

tree-core-backend icon tree-core-backend

A core component of TreeCore IDE to execute heavy computing task in backstage.

tree-core-bus icon tree-core-bus

A General Bus Generator which supporting AMBA, Wishbone, TileLink and ChipLink.

tree-core-cicd icon tree-core-cicd

A CI/CD environment for the processor simulation and verification.

tree-core-compiler icon tree-core-compiler

zodiac: A tiny statically typed, compiled system programming language which supports many modern features to build reliable and efficient software.

tree-core-cpu icon tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

tree-core-fpga icon tree-core-fpga

An Universal FPGA Framework for SoC Simulation and Verification

tree-core-ide icon tree-core-ide

:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

tree-core-ip icon tree-core-ip

A series of IP which has cycle-accurate, event-driven simulation models.

tree-core-rtos icon tree-core-rtos

a simple real-time operation system implement in C which support riscv ISA.

tree-core-sim icon tree-core-sim

A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

tree-core-soc icon tree-core-soc

A verilator based SoC simulation framework for TreeCore CPU.

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