mohamedtareq24 Goto Github PK

4_channel_logic_analyzer

FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA

555-watch

digital watch based on 555 timer IC and 7447 decoder 74160 BCD counter and 7 segment dispalys

asic_implementation_of_pulpino_soc

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

asics_design_diploma

RTL to GDSII flow of a low Power configurable multi clock digital system

asu-icl-low-cost-brucella-sensing-solution

EIS based solution for sensing Brucella in milk based on ESP32 low cost MCU with MATLAB in the loop affiliated with Ain Shams University IC lab supervised by professor Hani Fikry

asu_soc

c-polynomails-long-divider

dsp_custom_axi_ips

Work under progress.

ieee_asusb_2023_digital_design_workshop

ieeecusb_electronics_23_finalproject

This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented

my_verification_work

A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE

ode_solver_nios_ii

NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA

spi_memory_interface

The RTL for an SPI slave memory interface

the-drone

A repository for a quadcopter project