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Leo Moser's Projects

cace icon cace

Circuit Automatic Characterization Engine

caravel icon caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

chip-gallery icon chip-gallery

This is the repository where I store the layout for chips that I have designed.

cocotb icon cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cv32e40x icon cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

dffram icon dffram

Standard Cell Library based Memory Compiler using FF/Latch cells

gpi-test icon gpi-test

This is a test of cocotbs GPI interface.

iic-osic-tools icon iic-osic-tools

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

leosoc-gfmpw-1 icon leosoc-gfmpw-1

A simple dual-core SoC with true random number generators as payload.

ml_nlc icon ml_nlc

NLC table replacement based on ML

open_pdks icon open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

openlane2 icon openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

openram icon openram

An open-source static random access memory (SRAM) compiler.

pmod-levelshifter icon pmod-levelshifter

A bidirectional levelshifter designed in KiCad to control higher voltages on an FPGA

qspi-pmod icon qspi-pmod

A QSPI Pmod board designed in KiCad containing one Flash and two SPRAMs

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