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followers: 7.0 following: 43.0 repos: 51.0 gists: 1.0

Name: Mr Heap Allocator

Type: User

Bio: Let's make something elegant.

Twitter: MrHeapAllocator

Location: New York

Blog: https://www.linkedin.com/in/iparikshitdubey/

Hi there 👋

🔭 I’m currently learning Kernel development.
🌱 I’m working on my personal project OS One and looking to collaborate, please feel free to shoot an email if you are interested.
😄 Pronouns: he/him/his
⚡ Fun fact: I am a hardware designer too. 😉

Mr Heap Allocator's Projects

16-bit-cpu-design

Designed a 16-bit CPU architecture using VHDL. The architecture components include a CPU Controller; Instruction Register; a 16-bit ALU which implements two arithmetic functions, eight logical functions, and two shift operations. The generic memory of size 64-KB is also designed. The simulation was carried out using ModelSim. Synopsys Design Vision was utilized as the synthesis tool for this project

8-bit-microprocessor

Design and Implementation an 8-bit Microprocessor in Verilog. The design utilized sixteen 8-bit registers and one accumulator register. The data path was designed in a non-pipelined fashion. ModelSim was leveraged as a simulation environment for design.

a-star-visualizer-using-python

algoandds

Algorithm and Data structure codes in Python

algorithmic-stock-trading

algorithmictoolboxcodes

This repository contains the codes from courser course "Algorithmic Toolbox"

amazoncompetitordatabase

Database for Amazon competitors. The entity-relationship diagrams were constructed using MS Visio. The scripts in the database implementation were executed on SQL Management Studio. The design was overall normalized in 3rd Normal Form.

back-end-basics

bist-implementation

Designed and implemented the DFT tool in Verilog to add BIST capabilities to any given digital circuit. The components Pattern Generator (PG), Response analyzer (RA), and the BIST controller were designed to form a complete BIST circuit. The implementation of BIST circuitry was carried out on an Arithmetic Unit.