multimedia-processing Goto Github PK

arachne-pnr

Place and route tool for FPGAs

bsv_tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

digital-logic-design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

fpga-usb-device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

ghdl

VHDL 2008/93/87 simulator

hbird-e-sdk

Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/

hbird-sdk

OpenSource HummingBird RISC-V Software Development Kit

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

linter-veriloghdl

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

mp3_converter

Python browser automation for mp3' downloads from you tube

multimedia-database

multimedia-processing-description-language

「多媒體處理描述語言」(MPDL, Multimedia Processing Description Language)是將一部影片如何經由素材、製作流程與後製三項元素融合製作而成，但以程式腳本的方式描述一部影片的製作方式。

multimedia-processing-description-language-editor

針對開源項目「多媒體處理描述語言」(Multimedia Processing Description Language)所製作出來的編輯器，並搭配Git版本管理、機器學習、人工智慧、多人協作、自動處理等特性與目標開創新的影片製作流程。

multimedia-processing-description-language-server

multimediainfo

forked from laodifang/MediaInfo, Wolcome Pull Requests.

myhdl

The MyHDL development repository

nextpnr

nextpnr portable FPGA place and route tool

pint_iverilog

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

python-instruction-set-computer

「Python指令集處理器」(Python instruction set computer)是一個基於Python程式語言所製作出的高階指令集處理器，目的是使用邏輯閘的方式組成Python程式，讓處理器在運作的時候可以如Python一樣的簡潔、快速。

risc-v-single-cycle-cpu

A RISC-V 32bit single-cycle CPU written in Logisim

slang

SystemVerilog compiler and language services

verilog-fixedpoint

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

wavedrom.github.io

Digital timing diagram editor