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100-days-of-rtl-codekothavani

100-days-of-rtlchandrika

100-days-of-rtlpavan

100daysofrtlshashank

I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.

actions-drawio

Convert draw.io documents to jpeg, png, svg, pdf using drawio-batch.

af_sva_apb

AsFigo's opensource SVA IP for APB protocol + SVUnit tests on Verilator

apb_uvc_verilator

APB UVC ported to Verilator

apb_vip

Verification IP for APB protocol

aws_github_example

kjdkfjasjdlfjkasjdf

axi4_vip

Verification IP for APB protocol

best_coding_practices

Describes the best coding practices and guidelines

cache-memory-controller_project

This repo consists of my work on designing a simple efficient cache mem controller which can control the data between cache and cpu.

cpython

The Python programming language

digitaldesigncourse

github_experiment

Experimenting the Git and Github lab sessions

gpio_vip

Verification IP for GPIO protocol

i2c_vip

Verification IP for I2C protocol

i2s_vip

Verification IP for I2S Protocol

jtag_vip

Verification IP for JTAG protocol

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

nerd-fonts

Iconic font aggregator, collection, & patcher. 3,600+ icons, 50+ patched fonts: Hack, Source Code Pro, more. Glyph collections: Font Awesome, Material Design Icons, Octicons, & more

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-pdf

Converts the SystemRDL data into pdf Register specification

peakrdl-svh

Used for creating the systemverilog header files, which contains the defines for the registers

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pipecolor

A terminal filter to colorize output

pulpino_soc_uvm_testbench

UVM testbench for verifying the Pulpino SoC

python_course

Python basics

python_projects

To stores the projects based on python