nasirkhanpak Goto Github PK

2-1-mux-verification-using-uvm

this is for example to learn the UVM methodology

5-stage-pipeline-risc-v_isa

This repository contains 5 stage pipeline core on RISC-V ISA.

7-taskbar-tweaker

Windows Taskbar Customization Tool

acov

Generator of functional coverage tracking code for Verilog projects

amiq_eth

Library defining all Ethernet packets in SystemVerilog and in SystemC

amiq_i2c

Verification Component for I2C protocol

apb-uart-uvm-env

archery_game

Archery game developed in C

arduino-irremote

Infrared remote library for Arduino: send and receive infrared signals with multiple protocols

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asynchronous-fifo

Asynchronous fifo in verilog

autosva

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

awesome-embedded-software

:construction: attempt to create list of software (HW, libs, protocols, etc) for Embedded Systems

axi_bfm

AXI 总线验证 模块

baiduwp-php

PanDownload website replica

baremetal-c

Under the hood: Arm Cortex-M4 Bare Metal Embedded Programming in C

basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functi

bishengjdk-11-mirror

mirror of bishengJDK-11 https://gitee.com/openeuler/bishengjdk-11/tree/risc-v

burq-single-cyclic-core-risc-v

This is the single cyclic core based on RISC-V ISA code is in chisel language which is a module of Scala language.e

can-bus-controller

An CAN bus Controller implemented in Verilog

chatgpt

🔮 ChatGPT Desktop Application (Mac, Windows and Linux)

chip

An IDE and front-end EDA tool for Modern Hardware Design.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-beginners-guide-book

『Chiselで始めるFPGA電子工作』のサポートサイトです

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-seed.g8

chisel-study

ハードウェア構築言語Chiselでちょっとしたコードを書き溜めておくプロジェクト

chisel-template

Its an almost empty chisel template using sbt and makefile useful for making new chisel project

chisel-template-1

A template project for beginning new Chisel work

chisel-tests

Chisel Experiments