nblei Goto Github PK

2022_nsf_medium

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

academicpages.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

audio_pipeline

ILLIXR audio recording and playback pipelines

bitsad.jl

Bitstream computing got you a bit sad? Just use BitSAD!

bluez

My bluez tree.

data_structures

Some data structures in C

dimacs-parser

Utilities to parse files in DIMACS format which is the de-facto standard for input to SAT solvers.

dk

Hex files for dk

dl_algox

Implementation of Dancing Links data structure and Algorithm X

documents

Documents to transfer between school/home etc

dotfiles

My dotfiles

ece498

ECE498 ICC

ece498icc

eece381module2

emu8080

Intel 8080 emulator

examcalculator

exam calculator

flexicoresveryl

FlexiCores in Veryl HDL

get_gates_from_netlist

get gates from netlist

i3config

My I3 configuration

mason-registry

Core registry for mason.nvim.

mc6502

Cycle accurate MC6502 compatible processor in Verilog.

nsf_small_sensory_computing

Sensory Computing NSF Proposal

olfactory_asics

Olfactory Computing ASICs

program_options

Boost.org program_options module

pufs

Physical Uncloneable Functions RTL implementations

rhamt

Reslient Hash Array Mapped Trie

riscv-isa-sim

Spike, a RISC-V ISA Simulator

simple_cache

Simple (single bank) hardware cache model written in C for measuring hit/miss type statistics

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017