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assignments-aos

my assignment submissions for Advanced Operating Systems (CS G623 First Semester 2014-15)

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

cacti-6.0

ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write ports, and it can easily get the simulation result (like frequency, power consumption, and area... etc.).

cashmc

CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube

distributary

Dynamically changing, stateful data-flows for database-like storage.

dlrm

An implementation of a deep learning recommendation model (DLRM)

dramsim3

genomicsbench

A benchmark suite to study the performance characteristics of genomics applications

graph_lib

A library for graphs

hmctherm

a cycle-accurate simulator for hybrid memory cube with thermal analysis

iob-soc

RISC-V System on Chip Template Based on the picorv32 Processor

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

neethubal

Config files for my GitHub profile.

neethubal.github.io

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

riscv-isa-sim

Spike, a RISC-V ISA Simulator

rv8

RISC-V simulator for x86-64

sniper