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-tage-based-predictor-verilog-code

Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud

9444

9444 RISC-V 64IMA CPU and related tools and peripherals.

acg

Arbitrary Cell Generator enables parametrized grid-free circuit layout creation

activecore

Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)

ahblite2apb

AHBLite bus to APB4 bridge

ahblite_interconnect

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

align-public

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amc

AMC: Asynchronous Memory Compiler

analog-design-of-asynchronous-sar-adc

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

anfield

An incomplete RISCV-IM64 SoC

apb-uart-uvm-env

apb_spi_master

apb_sram

apb_uvc_verilator

APB UVC ported to Verilator

armleocpu

Multicore RISC-V CPU RV32IMA w/ MMU, Cache capable of booting Linux. Work in progress to execute first instruction

automata-synth

A framework for learning automata from legacy code for execution on FPGAs

ava-core

A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)

awesome-dv

Awesome ASIC design verification

awesome-semiconductor-startups

List of awesome semiconductor startups

awesomerisc-vresources

It contains a curated list of awesome RISC-V Resources.

axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

axi4_interconnect

AXI总线连接器

axi4lite_100mbps_mac

axi_dma

General Purpose AXI Direct Memory Access

berkeley-hardfloat

black-parrot-branch-predictor

Branch Predictor Optimization for BlackParrot

bonfire-cpu

FPGA optimized RISC-V (RV32IM) implemenation

brianhg-ddr3-controller

DDR3 Controller v1.50, 16 read/write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. HDMI video controller included.