openxiangshan Goto Github PK

berkeley-hardfloat

block-inclusivecache-sifive

coremark-pro

Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embedded microcrontrollers (MCU)

coupledl2

Open-source non-blocking L2 cache

cpu2006litewrapper

difftest

Co-simulation framework for Xiangshan

dramsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

edk2

EDK II

edk2-platforms

EDK II sample platform branches and tags

env-scripts

Scripts for XiangShan

force-riscv

Instruction Set Generator initially contributed by Futurewei

fudian

Open source high performance IEEE-754 floating unit

gem5

huancun

Open-source high-performance non-blocking cache

kvmtool

Stand-alone Native Linux KVM Tool repo

labeled-risc-v

nemu

nexus-am

ns-bbl

opensbi

RISC-V Open Source Supervisor Binary Interface

openxiangshan.github.io

penglai-sagittaverificationplatform

Sagitta_verification_platform from Penglai

penglaijiezi

Jiezi simulator from Penglai

perfui

qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

ready-to-run

riscv-arch-test

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-isa-sim

Spike, a RISC-V ISA Simulator