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force-riscv

Instruction Set Generator initially contributed by Futurewei

ralbot-html

Generate address space documentation HTML from compiled SystemRDL input

ralbot-ipxact

Convert compiled SystemRDL input into IP-XACT XML

ralbot-uvm

:honeybee:Generate UVM register model from compiled SystemRDL input

riscv-aia

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-compliance

riscv-count-overflow

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-iommu

The repo will be used to hold the draft non-ISA IOMMU specification under codevelopment by the IOMMU TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-state-enable

riscv-tee

riscv-test-env

riscv-tests

riscv-trace-spec

Working Draft of the RISC-V Processor Trace Specification

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.