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amba_axi_ahb_apb

AMBA bus lecture material

arm9-compatible-soft-cpu-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

arm9tdmi

A softcore processor with ARM9TDMI architecture

awgn_generator

FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method

axi-bfm

git clone of http://code.google.com/p/axi-bfm/

axi2apb

axi_spi_slave

bypass

Bypass domain, CIDR list. Block domain list.

chisel_bootcamp_amm

crc

Some knowledge about CRC.

greenlib

GreenLib official mirror, please use git.greensocs.com for issues and contributions

hdl

HDL libraries and projects

hoge_cic_filter

Implement of CIC Filter base on Hogenauer's Paper.

hw

RTL, Cmodel, and testbench for NVDLA

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

iverilog

Icarus Verilog

jesd204b

marss-riscv

Micro-ARchitectural Full System Simulator for RISC-V

matchlib

SystemC/C++ library of commonly-used hardware functions and components for HLS.

nios_case

Some study case of Altera NIOS core

nyuziprocessor

GPGPU microprocessor architecture

open_fir

openip

Open source IP collection

opentitan

OpenTitan: Open source silicon root of trust

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

poena

Config files for my GitHub profile.

poena.github.io

prbs

Some code for prbs

pulpino

An open-source microcontroller system based on RISC-V

reed_solomon_algorithm

Reed Solomon encode and decode algorithm research.