Comments (6)
Now I'm just wondering why rtt-target
actually need an explicit call 😄
from probe-rs.
@Tiwalun If we break on main, before the user code executes, will it not be a case of the RTT control structures have not yet been configured?
from probe-rs.
I think that's a good point on the difference between defmt-rtt and rtt-target - the former is statically configured (so it will be initialized by cortex-m-rt essentially before main starts), while the latter requires an explicit init call (after main starts).
from probe-rs.
That is a valuable distinction. Our handling and timing of attach should follow different paths then for the two.
I suspect this distinction might answer @Tiwalun 's question about "if we consciously decided to take a different approach".
from probe-rs.
Now I'm just wondering why
rtt-target
actually need an explicit call 😄
rtt-target works around the possibility of the debugger polling the rtt control block before its fully constructed. It does this by writing the segger string last. However, in practice, I'm not sure this workaround is entirely relevant because I don't think anyone has ever run into it. It might not be worth implementing this workaround, and falling back to how defmt initializes the control block.
from probe-rs.
It's actually a real world issue that we run into sometimes. But maybe if we do the breakpoint procedure we can mitigate it and get something more out of it even :)
from probe-rs.
Related Issues (20)
- Better recovery
- Design a lower level interface HOT 2
- Multicore support HOT 2
- Introduce a tier system for architecture support
- Make debug sequences a bit more configurable by making it possible to set them externally
- Automatic chip detection HOT 2
- Define resets and their expected behavior better
- CI tests
- Better documentation
- Make VSCode install probe-rs if it is not present HOT 3
- Clean out debugger code HOT 4
- Make the debugger a separate project that can debug x86
- Stable scripting API in the CLI
- Xtensa: `wait_for_core_halted` sets INTLEVEL to 1
- [feature request] Add pre-verify before flashing
- Fail to compile via cargo `error: failed to run custom build command for libudev-sys v0.1.4` HOT 2
- Typo in Stlink `swj_sequence` function
- STM32H745IIx RTT does not work unless both cores are running.
- Unable to flash STM32F303VCT6 discovery board: Timeout while erasing flash sector
- AVR support
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from probe-rs.