SEW-related error

[ralc88]

SEW-related error

[RALC88]

Dear minhoha,
That configuration corresponds to the riscv-v-spec-0.7.1 ?
In page 7 of the spec there is a table (Table 2. vtype register layout) where :
6:5 vediv[1:0] Used by EDIV extension
4:2 vsew[2:0] Standard element width (SEW) setting
1:0 vlmul[1:0] Vector register group multiplier (LMUL) setting
Then for vsew is from bit 2 to bit 4 (3 bits). This corresponds to vt(vtype,2,3) , which indicates that starts reading vtype in bit number 2 , and reads 3 bits.

In the case "if SEW=64, vsew will output 6", means that the switch case should enter to the default case and signal panic for all the apps which use 64-bits. But I have not seen that behavior.

I will do a double check to be sure. Are you using the compiler for version 0.7 ??

[RALC88]

Since there was no response, and I could not reproduce the error, the issue is closed.