randomreaper / pim-vhdl Goto Github PK
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My VHDL code
VHDL assertion in this lib must be formalized to distinguish between expected and unexpected warnings and ghdl-all.sh
must understand them.
As it is written in the VHDL:
-- FIXME : loose bytes when using ftdi_set_latency_timer(ftdi, 1), so
-- use ftdi_set_latency_timer(ftdi, 2).
bytes may be lost when using ftdi_set_latency_timer(ftdi, 1)
, this may be linked with #2.
There is a bug when small data transfers are too close (in the same direction) probably for RX and TX.
If you face this bug, the workaround for TX is to put the small packets in a buffer and send them at once, for RX, data should be read in a similar manner.
Since this bug is not in my use case, I won't fix it, but feel free to participate.
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