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bsg_accel

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

chipyard

An Agile Chisel-Based SoC Design Framework

chisel-minicpu

chisel-style-guide

A Style Guide for the Chisel Hardware Construction Language

chisel-template

A template project for beginning new Chisel work

chisel-tutorial

chisel tutorial exercises and answers

decimal

Arbitrary-precision fixed-point decimal numbers in go

decimalmultiplication

decimalmultiplication128-bit

decimalmultiplication64-bit

DecimalMultiplication64-bit

decimalmultiplicationaccelerator

decimaltestcase

Decimal Arithmetic Test Example

ecoflex-hdp

gcc

gpy

Gaussian processes framework in python

hgp

A Scalable Hierarchical Gaussian Process Classifier

lhsmdu

This is an implementation of Deutsch and Deutsch, "Latin hypercube sampling with multidimensional uniformity", Journal of Statistical Planning and Inference 142 (2012) , 763-772

lookingforseagrass

muffin-cupcake

classifying muffin and cupcake recipes using support vector machines

naist-thesis-tmpl-en

A modern LaTeX template for your doctoral dissertation or master's thesis of NAIST-IS.

path

riscv-llvm

SiFive's LLVM working tree

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

rocket-chip

Rocket Chip Generator

rocket-chip-rocc

This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.

rocket-rocc-examples

Tests for example Rocket Custom Coprocessors

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

rsd

RSD: RISC-V Out-of-Order Superscalar Processor