Comments (6)
Thanks @Hsiangkai for putting this RFC together.
I understand that vcopy_v
is needed when we want to copy only VL elements of the vector. My understanding is that a plain C assignment would copy it all (so the vector vehaves like a regular value here).
Regarding a question posed by @zakk0610 during our internal discussion, I understand reinterpret intrinsics will allow converting mask types to/from other integer types of LMUL=1. Also I presume reinterpret casts will allow reinterpretation between different types of the same LMUL (e.g. i32m1
and i64m1
), won't it?
from rvv-intrinsic-doc.
Oh... in fact SiFive’s Implementation vcopy is same as assignment in C, which is VL aware, the same issue for vector type is pointer dereference vs unit stride load/store, we implement its in VL aware too.
We might need to create a new issue to discuss about the behavior and limitation for vector type.
from rvv-intrinsic-doc.
If we support C assignment, should we support other C operators for scalable vector types? We should list the supported C operators in the RFC. In addition, what is the operating scope of C operator, VLMAX or vl? In SiFive's implementation, it is vl. The semantics is aligned to intrinsics design without vl argument.
from rvv-intrinsic-doc.
I agree we should support " converting mask types to/from other integer types of LMUL=1".
But I could not image why user want to reinterpretation between different types of the same LMUL, it is strange usage.
edited: we could discuss it in https://github.com/sifive/rvv-intrinsic-doc/issues/12
from rvv-intrinsic-doc.
Oh... in fact SiFive’s Implementation vcopy is same as assignment in C, which is VL aware, the same issue for vector type is pointer dereference vs unit stride load/store, we implement its in VL aware too.
We might need to create a new issue to discuss about the behavior and limitation for vector type.
We could discuss it in https://github.com/sifive/rvv-intrinsic-doc/issues/13.
from rvv-intrinsic-doc.
We will discuss the RFC in other issues.
from rvv-intrinsic-doc.
Related Issues (20)
- Question on using the intrinsics on mask registers HOT 7
- Confusion about intrinsic naming logic and Vlen setting HOT 3
- Fixed length attributes HOT 10
- Question about vmv.s.x and vmv.s.f's intriniscs with the suffix `m2_tu`, `m4_tu` and `m8_tu` HOT 5
- Vector floating-point moves translated into strided loads HOT 3
- New intrinsic apis
- Exposure of vlenb missing for vread_csr HOT 3
- Missing all variants of segmented load/store intrinsics HOT 1
- Privileged instructions generated by GCC and rvv-instrisics HOT 2
- Question about "If XLEN < SEW, the value from the scalar register is sign-extended to SEW bits." HOT 11
- are there intrinsics for the whole register load/store instructions? HOT 3
- What's the meaning of new_vl in Unit-stride Fault-Only-First Loads Functions? HOT 4
- How to deal with some unsupported interfaces on rv32? HOT 1
- Question about load mask intrinsics HOT 2
- Why use vleff instead of vle to implement the strncpy HOT 2
- Question about widening and reinterpreting inside a loop HOT 4
- Intrinsic Support for BF16 Extension HOT 7
- Maskedoff parameters in "xu" prototypes HOT 1
- question about intrinsic naming HOT 2
- Question about naming of overloaded policy load functions HOT 4
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from rvv-intrinsic-doc.