Comments (2)
... isn't that just the load/store intrinsics? (see the printiv64
/printfv64
in https://github.com/rdolbeau/EPI-test-codes-vector/blob/master/simplefft16-rvv/test_fft16_zgemv.c)
The 'easy' way for printf would be a vector 'Length modifier/Conversion specifiers' to signal vectors so that printf can deal with them directly. Would be convenient, but then users will request all the already existing modifiers (width, precision, display style, ...) and then request some brand new ones (field separator between vector lanes, ...) ...
from rvv-intrinsic-doc.
I agree with you. Vector store is enough.
from rvv-intrinsic-doc.
Related Issues (20)
- [Proposal] Support for C operators on RVV types HOT 12
- vget for fractional register doesn't exist HOT 10
- Constraint of vector types in Zve32* HOT 2
- [Requirement]: The RISC-V RVV vector intrinsic must include support for vector groups in the __riscv_vfredosum function HOT 4
- Type-relative overloads for vreinterpret, vlmul_ext, vlmul_trunc, etc. HOT 1
- How to use a class to wrap or derive from a sizeless vector type HOT 1
- Encode all the effects of vsetvl in the return type, for use in subsequent type deductions HOT 1
- Does `__riscv_v_intrinsic >= 1000000` imply overloaded intrinsics are supported?
- Create bibliography from reference section HOT 3
- Simple questions about inline assembly in vmv.x.s instruction HOT 2
- Asterisks are not subscripts
- the wrong result of "vmerge_vvm_i32m1" HOT 5
- ta,ma reduction destination with vl=0 HOT 1
- Clarify the consequences of vxsat not being handled by the intrinsics HOT 3
- Add a section with examples HOT 3
- Rename uses of {implicit,explicit}-frm into {Implicit, Explicit} FP rounding mode HOT 1
- Clarify the mapping of pseudo-intrinsics
- Clarify what float and double means HOT 1
- Fix authors in the document
- How to use LMUL in rvv-intrinsic? HOT 6
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from rvv-intrinsic-doc.