Comments (11)
Another arithmetic sequence is something like
__riscv_vwmaccu_vx(__riscv_vwaddu_vv(a, b), -1U, b)
from rvv-intrinsic-doc.
Right,
vrgather
can be used to do a zip, and I did include that in my message. But, for a situation where it's followed by a store, I'd expect a segmented store to be at least as good, given that, worst-case, hardware can always itself implement the unit-stride segmented store asvrgather
followed by a regular store (but of course a segmented store has the potential to be better too; and of course hardware is also free to do a clearly-suboptimal thing, but this would be pretty sad as then there'd be no situation ever where the segmented load/store instructions are best option).Of note is that clang compiles that example to a segmented store.
Yeah. Segment store should be good in hardware in most cases. But segment load not sure.
The example I shows is just to clarify how to use vmerge + vrgather simulate ZIP with compile option tunning.
Actually, current RVV compiler no matter GCC or Clang, is always using segment load/store by default:
https://godbolt.org/z/jseq14fMf
from rvv-intrinsic-doc.
This is indeed a messy thing in RVV; there's no RVV instruction for doing a zip in-register, so you have to emulate it with a vrgather
(or, for ≤32-bit elements, there's also the option of doing some widening arith, something like vwadd_wv(vsll_vx(vzext_vf2(a), width), b)
, which might be faster or slower depending on hardware).
But of note is that if you need to immediately store the result, a segmented store can be used (e.g. __riscv_vsseg2e32_v_i32m1x2
)
from rvv-intrinsic-doc.
Another arithmetic sequence is something like
__riscv_vwmaccu_vx(__riscv_vwaddu_vv(a, b), -1U, b)
I'm pretty sure this should use
vzext
instead of thevwmaccu
. Alternativelyvadd.vv
&vwmul.vx
.
No, vwaddu is correct - the idea is that the -1 * b
does (2^n-1) * b
and then the extra b+
makes it exactly (2^n)*b
, and we also add a
while at it and thus need all adds to work in the wider space as they're actually all adds, not bitwise magic. (I too thought it was wrong until I threw it into a SAT solver, and it accepted the widening add but not a zext)
from rvv-intrinsic-doc.
I am not sure whether it is a good example:
https://godbolt.org/z/rMK898G1d
For ARM SVE, use zip to interleave the data.
For RVV, we can use vid + vand + vmseq + vmerge with mask to interleave the data.
For example:
vid v (01234....)
vand.vi v , 3 -> (012012012012....)
Then you can use the AND result to generate 101010101010...mask with:
vmseq.vi v, 0
Then you can use the AND result to generate 010101010...mask with:
vmseq.vi v, 1
Then you can use the AND result to generate 001001001001...mask with:
vmseq.vi v, 2
You can use those masks + vmerge to interleave data if you don't want to segment load/store (Which is expensive instructions in hardware).
from rvv-intrinsic-doc.
@zhongjuzhe An ARM zip does a transform like src1=[a,b,c,d], src2=[e,f,g,h]
to zip1=[a,e,b,f], zip2=[c,g,d,h]
, which changes the indices of elements (e.g. e
was src2[0]
but at zip1[1]
in the result). vmerge
s alone cannot achieve that. Though, yes, if the rearranging is avoidable/unnecessary, it's beneficial to avoid it.
from rvv-intrinsic-doc.
@zhongjuzhe An ARM zip does a transform like
src1=[a,b,c,d], src2=[e,f,g,h]
tozip1=[a,e,b,f], zip2=[c,h,d,h]
, which changes the indices of elements (e.g.e
wasy[0]
but atzip1[1]
in the result).vmerge
s alone cannot achieve that.
No. I am not saying that vmerge alone achieve zip in ARM SVE.
vmerge is generating the index for vrgather.
Actually, vmerge + vrgather. The example has explicitly shows that:
https://godbolt.org/z/rMK898G1d
from rvv-intrinsic-doc.
@zhongjuzhe An ARM zip does a transform like
src1=[a,b,c,d], src2=[e,f,g,h]
tozip1=[a,e,b,f], zip2=[c,g,d,h]
, which changes the indices of elements (e.g.e
wassrc2[0]
but atzip1[1]
in the result).vmerge
s alone cannot achieve that. Though, yes, if the rearranging is avoidable/unnecessary, it's beneficial to avoid it.
Oh. Sorry. I realize that I am showing incorrect example:
https://godbolt.org/z/vnboG1rvz
This is the example using vmerge+vrgather.
vmerge generate the index. vrgather shuffle the vector.
from rvv-intrinsic-doc.
Right, vrgather
can be used to do a zip, and I did include that in my message. But, for a situation where it's followed by a store, I'd expect a segmented store to be at least as good, given that, worst-case, hardware can always itself implement the unit-stride segmented store as vrgather
followed by a regular store (but of course a segmented store has the potential to be better too; and of course hardware is also free to do a clearly-suboptimal thing, but this would be pretty sad as then there'd be no situation ever where the segmented load/store instructions are best option).
Of note is that clang compiles that example to a segmented store.
from rvv-intrinsic-doc.
@zhongjuzhe @dzaima Thanks! I'll check that out.
from rvv-intrinsic-doc.
Another arithmetic sequence is something like
__riscv_vwmaccu_vx(__riscv_vwaddu_vv(a, b), -1U, b)
I'm pretty sure this should use vzext
instead of the vwmaccu
. Alternatively vadd.vv
& vwmul.vx
.
from rvv-intrinsic-doc.
Related Issues (20)
- [Requirement]: The RISC-V RVV vector intrinsic must include support for vector groups in the __riscv_vfredosum function HOT 4
- Type-relative overloads for vreinterpret, vlmul_ext, vlmul_trunc, etc. HOT 1
- How to use a class to wrap or derive from a sizeless vector type HOT 1
- Encode all the effects of vsetvl in the return type, for use in subsequent type deductions HOT 1
- Does `__riscv_v_intrinsic >= 1000000` imply overloaded intrinsics are supported?
- Create bibliography from reference section HOT 3
- Simple questions about inline assembly in vmv.x.s instruction HOT 2
- Asterisks are not subscripts
- the wrong result of "vmerge_vvm_i32m1" HOT 5
- ta,ma reduction destination with vl=0 HOT 1
- Clarify the consequences of vxsat not being handled by the intrinsics HOT 3
- Add a section with examples HOT 3
- Rename uses of {implicit,explicit}-frm into {Implicit, Explicit} FP rounding mode HOT 1
- Clarify the mapping of pseudo-intrinsics
- Clarify what float and double means HOT 1
- Fix authors in the document
- How to use LMUL in rvv-intrinsic? HOT 6
- Mismatched bfloat16 autogenerated files HOT 3
- Freeze the specification HOT 1
- `vfirst` and `vcpop` return types unexpectedly changed HOT 1
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from rvv-intrinsic-doc.