Calling convention for vector arguments

[riscv-non-isa]

Calling convention for vector arguments

[rofirrim]

Hi @PkmX thanks for the proposal. Seems reasonable.

In the EPI project we implemented the following interim calling convention:

Registers v0 and v16...v23 can be used to pass vector values.

The process is as follows (parameters would be processed in the order of the C declaration):

• mark registers v0 and v16...v23 as free.
• if the parameter is a mask type and v0 is free, then assign the parameter to v0 (mark the register as used)
• if the parameter does not have mask type or it does have mask type but v0 is not free then, use the following algorithm
  • determine the register group size (RGS) of the type
  • find the lowest numbered register vX in the set v16...v23 such that the register is free and the RGS divides X. If there are RGS consecutive free registers (starting from and including vX) then assign all of them to that parameter (mark all the registers as used)
  • if there are no free registers eligible under the case above, then the vector is passed via the stack.

We initially believed it made sense to have callee-saved registers, hence the very limited range from v16 to v23. However the experience so far is that it may not be very valuable to have callee-saved registers (we could have them in an alternative, more specialized, calling convention such as one used by a vectorizer). The algorithm also prioritizes the mask to be in v0 (if any).

If we take the above algorithm and we use v0, v1...v31 (instead of v0, v16...v23) then I think that would be similar to your proposal. It also addresses the question of the holes you make at the end.

I wouldn't be very worried about the 3 m8. In general, if there is a mask around, 3 is also the maximum number of useable m8 register groups (because the mask in v0 prevents us from using the register group v0...v7).

One thing missing from the algorithm above is that segment vectors. In that case I understand X needs to divide RGS but we need X * nf registers available. Also, as you mentioned, fractional LMULs imply a RGS=1.

[ebahapo]

I think that the merger of proposals resulting in v0 and v1..31 as very interesting, including filling prior registers after an argument with LMUL > 1. However, IMO, 3 arguments is the practical minimum and more than this enters in the "nice to have" territory, which leaves just one m8 register available for consideration for callee saved ones, seemingly too few to make much of a difference.

Therefore, methinks that it's rather premature to nail down the calling convention. I'd prefer to have a working implementation upstream so that we can then model the best calling convention, especially on the issue of callee saved registers.

[zakk0610]

@PkmX @rofirrim please take a look the calling convention PR. riscv-non-isa/riscv-elf-psabi-doc#171

[eopXD]

This is discussion ongoing in the PSABI working group and out of scope of this repository. Closing the issue.