Make reduction more flexible

[riscv-non-isa]

Make reduction more flexible

[zakk0610]

The purpose of dst is used to preserve the tail elements. Why does this only support m1 type?
The scalar only use the first element. Why does this only support m1 type?

I guess it's history reason because rvv 0.8 does not support fraction lmul.

I prefer to keeping the original design, in your case, we can use int8_t vmv_x_s_i8m1_i8 (vint8m1_t src); to extract first element from m1 vector (reduction result), and use vint8m8_t vmv_s_x_i8m8 (vint8m8_t dst, int8_t src); to insert reduction result to any vector type you want and keep tail elements.

Do worry the performance, ideally compiler can do optimization for you.

[nick-knight]

I prefer to keep m1 type for the dst and scalar operands. In my opinion, this most closely matches the spec:

The scalar input and output operands are held in element 0 of a single vector register, not a vector register group, so any vector register can be the scalar source or destination of a vector reduction regardless of LMUL setting.

As an aside, another way to access the result of the reduction without loss of decoupling between scalar and vector instruction pipelines (when applicable) is just to use vrgather.vi dst, src, 0.

[nick-knight]

Just checking in on this open issue. I'm still in favor of the current approach, using m1 for dst and scalar operands.

I agree with @zakk0610 that this complicates the use-case of writing the reduction to the first element in an LMUL > 1 group. In principle, a compiler could fuse the scalar <-> vector copies by intelligently allocating the reduction's destination register. However, I don't think this is a terribly common use-case, so I suspect that implementers will not prioritize this optimization. If users complain, we could always add additional intrinsics following @HanKuanChen's suggestions.

Alternatively, we could implement register group fission/fusion, e.g.,

vint8m1_t fission_int8m2_m1_0 (vint8m2_t); // return zeroth vector register in group
vint8m1_t fission_int8m2_m1_1 (vint8m2_t); // return first vector register in group

which make the copies more obvious to both the user and the compiler. I think I proposed something like this many months ago, but was not in favor of it because of the "SLEN issue", which is no longer an issue.

[eopXD]

This is a good feature to consider, let us settle a version first and revisit this in the future.

[sh1boot]

How about extendingvget_u8m1 to act as vlmul_ext_u8m1 when receiving mf types, and the complement for vset_u8m1? (don't forget to include identity transforms)

Then the caller can convert anything to m1 and back around the reduction, in a type-agnostic way.