riscv-spec Goto Github PK
Type: Organization
Location: China
Type: Organization
Location: China
The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
RISC-V Assembly Programmer's Manual
Working draft of the proposed RISC-V Bitmanipulation extension
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
RISC-V cryptography extensions standardisation work.
Working Draft of the RISC-V Debug Specification Standard
Dot-Product Extension
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
Non-ISA IOMMU specification developed by the IOMMU TG.
RISC-V Instruction Set Manual
Working Draft of the RISC-V J Extension Specification
A matrix extension proposal for AI applications under RISC-V architecture
RISC-V Opcodes
RISC-V Packed SIMD Extension
PLIC Specification
RISC-V Architecture Profiles
Documentation for the RISC-V Supervisor Binary Interface
RISC-V SMBIOS Type 44 Spec
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.
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