Comments (6)
Looks like at least I need to also read mtopei
because that's only readable with an IMSIC.
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If someone could double check my logic at https://github.com/riscv/riscv-openocd/pull/815/files#diff-b4aa16f9e42cb8f0934baa7c8e0ec9c70a369bef98b99b26ae2e896c8aa95d6aR5402 that'd be very helpful.
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Presumably by accessing extension state you mean writing a CSR and seeing if the new value is accepted. For a debugger, that means:
- Read the CSR
- Write a new value
- Read it back to see if the value was accepted
- Write back the original value, so we don't interfere with the running code.
That's quite a process. I much prefer a single read (and even that will grow out of control if the debugger has to do a read for every extension that adds CSRs). Hopefully some day Unified Discovery can streamline this process.
Personally I'm only interested in whether the CSRs are implemented or not (so the debugger can show them to the user or not.) Would it still be necessary to try to access the state to see which CSRs are implemented?
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Personally I'm only interested in whether the CSRs are implemented or not (so the debugger can show them to the user or not.) Would it still be necessary to try to access the state to see which CSRs are implemented?
It depends on what the goal is. If the goal is to show that miselect
/mireg
are implemented then just accessing them suffices. If the goal is to show that the IMSIC is implemented based on existence of miselect
/mireg
then it may not be sufficient as these may be implemented to support a different extension than IMSIC. From the PR you posted seems like you are discovering mtopi
and using that to infer existence of miselect
/mireg
as well as AIA. That sounds okay to me.
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It depends on what the goal is. If the goal is to show that miselect/mireg are implemented then just accessing them suffices.
That is my goal. Thanks for looking over my PR.
I imagine a more sophisticated debugger would like to show whether IMSIC is supported.
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Related Issues (20)
- How to distinguish APLIC interrupt in MSI mode? HOT 4
- About the "sticky" property of sip. HOT 1
- Are priorities of virtual interrupts configurable to HS-mode through iprio array? HOT 3
- Can interrupt identity >63 cause a trap in non virtualized mode? HOT 2
- Does SEI in VS mode use default priority? HOT 2
- Why the priority of the third candidate of vstopi is 256? HOT 7
- About the possibility of IOMMU examining ie bit before sending notify MSI.
- local interrupts in sip and vsip may be cleared when other CSRs change
- mvien[1] HOT 1
- Conflict register model between MVIEN and HVIEN HOT 1
- MVIP.STIP HOT 2
- Optional setting of interrupt pending when writing sourcecfg? HOT 1
- Is there any requirement about the speed of arbitration or the interrupt infomation transfer? HOT 5
- ASCII doc broken text HOT 3
- Clarify "Access control by the state-enable CSRs" HOT 2
- How to define NMI in AIA architecture? HOT 1
- Does mstateen0[58]=0 take precedence over hstatus.VGEIN=0? HOT 1
- How to distinguish IPI and external interrupt if using IMSIC to accomplish IPI
- Should virtual supervisor domain be implemented in APLIC while hypervisor (virtual supervisor) is supported?
- What's the value of stopi.IPRIO when using mvien and mvip to generate a SEI that traps to S mode?
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