Comments (7)
Your example is correct. A read of a *topi
or *topei
CSR always returns the most recent information available.
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@yichanfeng, I do not understand the scenario you describe. Software doesn't know what the external interrupt is until it reads *topei
(which it should also write at the same time to claim the interrupt). Only by reading *topei
does software learn the priority of the interrupt. So, what is this?:
If a hart asks IMSIC for the interrupt arbitration, leading a trap handler to a lower priority interrupt handling (e.g. IID=4)
I don't recognize that step, which you say precedes reading *topei
to claim the interrupt.
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@jhauser-us
Thanks for your reply.
Yes, SW doesn't know what the external interrupt is until it reads *topei.
I am asking if HW needs to retain the older value of non-zero *topei until SW reads its value in the trap handler when the following scenario occurs.
- In the machine-level interrupt file of IMSIC, interrupt 4 (ID = 4) is pending-and-enabled. Then, the hart receives the external
interrupt and traps to M-mode. - Before SW executes the CSR instruction to read mtopei in the trap handler, the interrupt 1 (ID = 1, has higher priority) of
machine-level interrupt file becomes pending-and-enabled due to an MSI write. - When SW executes the CSR instruction in the trap handler,
the read value of mtopei will be 0x10001 (ID = 1, Prio = 1) instead of 0x4004 (ID = 4, Prio = 4).
=> Does this result match expectation (always return the latest value) ?
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Thanks for your reply.
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Hi @jhauser-us! I also have a question about *topei. What should the expected or suggested behavior be when we read/write the *topei while eidelivery=0? Should it assume that there are no valid external interrupts when eidelivery=0, causing the IMSIC to ignore the *topei access and only read it as 0? Or should it retain its original behavior, allowing harts to read/write the *topei, clean the highest priority eip pending bit, and only prevent the *EIP from being sent to harts?
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An interrupt file's eidelivery
register has no effect on a *topei
register. See new issues #56 and #57.
Note the similarity also with what the AIA spec says about the *topi
CSRs:
The value of
mtopi
is not affected by the global interrupt enable MIE in CSRmstatus
.
The value of
stopi
is not affected by the global interrupt enable SIE in CSRsstatus
.
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@jhauser-us Thanks!
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Related Issues (20)
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- Are priorities of virtual interrupts configurable to HS-mode through iprio array? HOT 3
- Can interrupt identity >63 cause a trap in non virtualized mode? HOT 2
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- mvien[1] HOT 1
- Conflict register model between MVIEN and HVIEN HOT 1
- MVIP.STIP HOT 2
- Optional setting of interrupt pending when writing sourcecfg? HOT 1
- Is there any requirement about the speed of arbitration or the interrupt infomation transfer? HOT 5
- ASCII doc broken text HOT 3
- Clarify "Access control by the state-enable CSRs" HOT 2
- How to define NMI in AIA architecture? HOT 1
- Does mstateen0[58]=0 take precedence over hstatus.VGEIN=0? HOT 1
- How to distinguish IPI and external interrupt if using IMSIC to accomplish IPI
- Should virtual supervisor domain be implemented in APLIC while hypervisor (virtual supervisor) is supported?
- What's the value of stopi.IPRIO when using mvien and mvip to generate a SEI that traps to S mode?
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