Locking idioms are incomplete

[riscv]

Locking idioms are incomplete

[aswaterman]

(Just providing context:) glibc's low-level locking code seems to use CAS to acquire locks and swap to release them.

[aswaterman]

I think all there is to say in the spec is that some more complex locks will be implemented with LR/SC. The only interesting thing about those sequences is how to set the AQ/RL bits on the two operations; while I think it will suffice to set AQ on a lock-acquiring SC and RL on a lock-releasing SC, we'd rather wait til the memory model discussion is more complete before writing that up.

[arkflpc]

I think that lock elision isn't compatible with LR/SC mechanism. Elided store wouldn't invalidate reservations held by other harts after LC instruction and SC would succeed. It would made LR/SC suffer from ABA problem.

[sorear]

There are a lot of misconceptions about ABA problem. LR/SC only has an expressiveness advantage over CAS if unrelated memory accesses are allowed to occur between the LR and the SC; RISC-V forbids this so RISC-V LR/SC is already precisely equivalent to CAS..

[kasanovic]

Regarding ABA - in the case where there is a single word being accessed, then LR/SC will abort if a second hart rewrites the same value as is currently in memory to the single word under reservation by a first hart. CAS will not detect this. This is admittedly a limited case but does mean LR/SC is not equivalent to CAS for ABA.