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stnolting avatar stnolting commented on May 22, 2024

Good idea!
I would add another "generic" category and define some points how to categorize a certain core:

  • FPGA: Core maybe uses FPGA-specific primitives/macros/attributes; scripts for certain synthesis flows; example top entity for certain FPGA dev board; ...
  • ASIC: Core maybe uses stuff that is not very common / bad practice on FPGAs like clock gating or latches; ...
  • Generic: Plain VHDL/Verilog/SystemC/you-name-it; no primitives/macros/attributes/etc. at all; technology-independent

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AESASH avatar AESASH commented on May 22, 2024

I second that

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stnolting avatar stnolting commented on May 22, 2024

I have just studied the new RISC-V compliance test framework v2 for porting it. Now that the new version has been officially released, how about adding a new column/category "RISC-V compliance" to show which tests (like rv32i_m/I, rv32i_m/M, ...) of the compliance framework a certain core passes? 🤔

from riscv-cores-list.

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