Question

[robseb]

Question

[robseb]

Kraj’s BSP layer is designed to fulfill the requirements and concept of Open Embedded and the Yocto project. My version is designed to try to fulfill Intel’s EDS concept.
In the next weeks I will upload driver-recipes for HPS-to-FPGA interaction. I will merge and extend by https://github.com/robseb/meta-rstools to this BSP-layer. In addition, I’m working on a SD-image creating tool that can replace the old Altera script “make_sdimage.py” that will be compatible with Intel EDS 19.1 and this layer (current solution: https://github.com/robseb/rsyocto/blob/rsYocto-1.03/doc/guides/6_newFPGAconf.md). I think then will be major differences noticeable.
Thank you for your question.

[robseb]

Yes, my Yocto layer don’t generate the secondary bootloader (u-boot) because with Intel’s EDS concept should be the primary and secondary bootloader generate within Intel EDS. Intel uses an optimized version of u-boot for their SoC-FPGAs.
I descript the complete build process in these following repositories (EDS Version 18.1). Inside the SD-card folder of rsYocto are the final bootloader files available, as well.
https://github.com/robseb/HPS2FPGAmapping
https://github.com/robseb/rsyocto

[joaoflnedap]

Thanks for replying and congrats for the initiative. I should give a try on approach sometime, and who know, help you out with some stuff.

Just another question: I see that you don't have the u-boot recipes as from kraj. Is that you are using u-boot as it is? Or how do you integrate your own?