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16_bit_adder

this is my Logic Design midterm Project

8bit-carry-lookahead-adder

A hardware implementation of an adder which is faster than the basic ripple carry adder

8pointdct_verilog

Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algorithms have been proposed over the last couple of decades to reduce the number of computations and memory requirements involved in the DCT computation algorithm. One of the algorithms is implemented here using Verilog HDL.

academic-writing-check

check for passive words, weasel words, duplicate words, typographical errors and words strunk & white don't like

approximate-1d-dct-architecture

This is a Verilog implementation of pipelined architecture for the computation of 1D 8-point DCT. This is an approximate architecture which uses only 12 adders and no multipliers for the whole computation.

bash-it

A community Bash framework.

bashtop

Linux resource monitor

cla-adder

Carry lookahead adder(32 bit) verilog code

config-ubuntu

Quickly Setup Ubuntu Desktop or Server with all-in-one Bash Scripts.

dbms-shell-script

database management system using shell scripting

digital_adders_verilog

32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog

ecen325finalproject

Repository for the ECEN 325 Final Project - CMOS Amplifier

gemini

Gemini is a modern LaTex beamerposter theme 🖼

hospital-management

Written in Java using Netbeans and MySQL

infufrgs

Latex templates for documents of INF/UFRGS

jpegencode

JPEG Encoder Verilog

latex-course-summary-template

A Latex summary / cheatsheet template for STEM subjects

layout-design-for-an-8-bit-microprocessor

Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS VLSI technology on Tanner EDA toolchain.

layout-design-of-an-8x8-sram-array

The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.

library-management

Library Management System using Java and MySQL

menu-bash

Creating sub menu in bash

modeling-of-10-bit-pipeline-adc-and-10-bit-dac

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

modeling-of-4-bit-flash-adc-and-4-bit-dac

This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

report

Report

rodrigowra

Config files for my GitHub profile.

rodrigowra.github.io

roofitcheatsheet

Latex BAPoster for RooFit Cheatsheet

ubuntu-server-setup

A setup script for Ubuntu servers

verilog-adders

Implementation of different types of adder circuits

verilog-adders-1

Implementing Different Adder Structures in Verilog