Comments (1)
shioyadan
commented on July 22, 2024
Hi,
RSD does not have any mechanism specifically designed to protect against such attacks. However, I think that RSD in its default configuration is unlikely to be vulnerable to such attacks because it is a relatively small out-of-order processor and has low cache miss latency. If you want such attacks to work on RSD, I recommend that you experiment with some of the above parameters modified (e.g., increasing the size of the ROB and memory access latency).
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Related Issues (20)
- error running the Makefile.verilator.mk HOT 3
- Off by one error in leading 0 count loop? HOT 1
- cannot convert ‘const VlWide<92>’ to ‘const uint32_t (&)[92]’ {aka ‘const unsigned int (&)[92]’} HOT 10
- wrong pointer used for poping btb queue HOT 2
- Wiki issue HOT 2
- Error when run in verilator: no viable conversion from 'const VlWide<92>' to 'const uint32_t [92]' HOT 2
- Report 'Memory address 0x1e38 is invalid' when running helloworld.elf in spike HOT 4
- PC becomes 0x00000000 after jump to 0x80000000 to execute auipc instruction HOT 7
- [Bug Report] SD bit in mstatus doesn't update when FS=11 HOT 3
- [Bug Report] RSD doesn't update mstatus after `mret` instruction HOT 3
- [Bug Report] `fflags` records the accumulated status incorrectly HOT 1
- [Bug Report] Incorrect upward rounding result of fsub.s instruction HOT 3
- Cache and BP Disable Possible Way HOT 6
- [Bug Report] OF flag bit in fflags is not set correctly after fdiv.s instruction HOT 1
- [Bug Report] RSD didn't update fflags.NX correctly after fnmadd.s instruction HOT 1
- [Bug Report] `fflags.NV` is not set correctly after `fsqrt.s` instruction HOT 1
- [Bug Report] `fflags.UF` is not set correctly after `fdiv.s` instruction HOT 1
- [Bug Report] `fflags.DZ` set incorrectly after `fdiv.s` instruction HOT 3
- [Bug Report] Wrong sign bit when 0 is multiplied by a negative number HOT 3
- [Bug Report] Wrong result of `+0` minus `+0` HOT 9
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