alu-with-class-based-tb-sv

A verification environment for an ALU using class-based testbench in `Systemverilog`

aptproject

async-fifo

An Asynchronous FIFO Design that contains synchronizers to avoid metastability that may occur due to full and empty flags

blinking_led_control

This project controls a LED that blink through variable PWM signal created by a timer, and defined by the LED driver user.

circuitd_na_solver

computer-architecture-labs

cs-video-courses

List of Computer Science courses with video lectures.

elevator-controller

An Elevator controller implemented in `VHDL` as an `FPGA` Design Internship GP

finalizing-chip

fpga-labs

gesture_hero

Gesture Hero is a hand gesture classification system that's build to differentiate between hand gestures representing numbers from 0-5.

github-slideshow

A robot powered training repository :robot:

logic-design-cad

mars-exploration

Course Name: Data Structures and Algorithms

museum_app

neural-networks-labs

os-simulator

This is the final project for Operating Systems course which we build a simulator for the OS kernel like process management and memory management.

risc-processor

Five-stages pipeline processor using verilog

rsa-encrypted-chat

rufaida-kassem

search-engine

smart-elevator

spi-implementation

statistics

vlsi-adders-mania

wild-run