Name: Ruochen Dai
Type: User
Company: University of Florida
Bio: Ph.D. candidate at the UF, majors in hardware security, formal verification, ASIC, computer architecture, and embedded system.
Twitter: ruochen20
Location: Gainesville
Ruochen Dai's Projects
ABC: System for Sequential Logic Synthesis and Formal Verification
american fuzzy lop - a security-oriented fuzzer
A curated list of awesome Fuzzing(or Fuzz Testing) for software security
无它术,唯勤读书而多为之,自工
Code repository for Coppelia tool
follow me to study modern c++
:books: Solutions for C++ Primer 5th exercises.
In this paper, a series of Ring Oscillators has been wired in different ways to form Ring Oscillator PUFs to find out the RO PUF which has a better quality. Thus, three different routing methods are proposed and developed , software automatic routing design, 1D and 2D hard-macro array design. And the quality factors including uniqueness, reliability and uniformity are analyzed
This project implements a 32-bit MIPS processor with forwarding and hazard detection module
In this report, we implement an accelerated convolution calculator based on Xilinx Zynq. We divide whole process into 4 key steps(DRAM read/write Interface, Convolution Pipeline, Smart Buffer and Kernel Buffer)
The SoC used for the beta phase of Hack@DAC 2018.
The HW-CBMC and EBMC Model Checkers for Verilog
IFLOW: Customizable Static Taint Analysis
JSON for Modern C++
KLEE Symbolic Execution Engine
Seeding fuzzers with symbolic execution
KLEESpectre is a symbolic execution engine with speculation semantic and cache modelling
Linux Device Drivers 3 examples updated to work in recent kernels
LLVM IR入门指南
Providing a software model of the TI MSP430
PROMPT: API model guided symbolic execution for component-level analysis
Python-based Hardware Design Processing Toolkit for Verilog HDL
QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
爬取菜鸟教程网站并转PDF__python_crawer_by_chrome
Scala based HDL
Sudoku Solving With Backtracking and SMT Solver in C