sahilmaurya007 Goto Github PK

-xininx-vivado-alternative-litex-

Build your hardware, easily!

a-primer-for-physical-design-automation

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

analog-design-of-asynchronous-sar-adc

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

arpitsinghyadav.com

brice-columber-cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

chipcraft---mest-course

circuitops-openroad-iitg

detect-waste

AI to Combat Environmental Pollution - detecting plastic waste in the environment to combat environmental pollution and promote circular economy (Deep Learning, PyTorch)

digital-asic-lab

Verilog Codes for various Design

dockerize-eda-eda-tools-

[WIP] Dockerize Synopsys/Cadence EDA tools

dynamatic-eth-zurich-open-source-xilinx-vivado-

ee628

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects

free-range-vhdl-book

Latex source files of the open-source book FREE RANGE VHDL

gdsfactory-generic-pdk

Generic Process Design Kit for Gdsfactory

lambdalib

Hardware abstraction library

layout-design-of-an-8x8-sram-array

The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.

learn-quantum-computing-with-python-and-q-qsharp-

Companion code for Learn Quantum Computing with Python and Q# Book by Dr. Sarah Kaiser and Dr. Cassandra Granade 💖

learn-riscv-from-basics-

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

linuxtest

lumos

Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor

matlab-simulink-challenge-project-hub

This MATLAB and Simulink Challenge Project Hub contains a list of research and design project ideas. These projects will help you gain practical experience and insight into technology trends and industry directions.

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

qflow

This repo is test for qflow opensource

raptor-open-source-fpga-

Raptor end-to-end FPGA Compiler and GUI

research-internships-for-undergraduates

List of Research Internships for Undergraduate Students

ripes-iit-roorkee-risc-simulator-

A graphical processor simulator and assembly editor for the RISC-V ISA

rram_compiler

This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London

sahil-maurya-website

Welcome to my profile