searsm8's Projects
Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.
Use Simulated Annealing heuristic to obtain layouts for standard cell layouts
Perform Simulated Annealing heuristic on a standard cell layout.
Algorithms which solve the channel routing and switchbox routing physical design problems.
Deep learning toolkit-enabled VLSI placement
Scripts to perform Design Space Exploration (DSE) using CyberWorkBench High-Level Synthesis tool
Program which implements Fiduccia–Mattheyses partitioning algorithm
Code for the International Symposium of Physical Design (ISPD) 2020 Contest Objective is to provide heuristic solutions for Cerebras' Wafer Scale Engine (WSE)
Simple implementation of LeNet using PyTorch
An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.
MLIR Sample dialect
Verilog project to implement an ASIC chip from specification to tape out. Performs audio filtering, known as the Mini Stereo Digital Audio Processor (MSDAP)
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Day-to-day log files of my PhD research
RePlAce global placement tool
Config files for my GitHub profile.
A collection of useful verilog modules
Vitis In-Depth Tutorials