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alu_uvm

UVM Test bench for a 8-bit ALU

amba_apb

To design test bench of the APB protocol

amba_axi_ahb_apb

AMBA bus lecture material

aproximated-uvm

This repository contains a proposal UVM testbench for aproximated circuits.

arm_watchdog

Verification IP for Watchdog

autonomus_car

autonomus_car

awesome-dv

Awesome ASIC design verification

axi

VIP for AXI Protocol

basic-uvm-env

Basic UVM Environment

basic_uvmc

A simple testbench with two refmods using UVM Connect

combinator-uvm

UVM Testbench For SystemVerilog Combinator Implementation

ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

design-and-verification-of-mcdf-phase3

design-and-verification-of-MCDF-phase3

design-verification

UVM and Systemverilog based test benches for functional verification of a RAM module

eda-log-colorizer

🎨 Colorize your boring EDA logs

elen613

Code for ELEN613: SOC Verification

env-mult-clk-domain

Environment for multiple clock domains

essveepy

Tools for interfacing between Python and SystemVerilog.

fall-detection

Lightweight fall detection based on human pose estimation

fcfs_arbiter_design_and_verification

Design and verification of first come first serve arbiter

fifo_tb_uvm

Self learnt example to write a UVM based TB. (Under construction).

fpga-design-with-systemverilog

SystemVerilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff, always_comb) and others allow modeling of RTL designs easily, and with less coding.

fstdumper

Verilog VPI module to dump FST (Fast Signal Trace) databases

gaia

Generate UVM testbench framework template files with Python 3

gen_uvm

EasierUVM from Doulos now written in Python for easier UVM with framework and template generator

hackathon

hf-risc

HF-RISC SoC

isp_uvm

A Framework for Design and Verification of Image Processing Applications using UVM

mult-dut-parl-stim

Multiple DUT with parallel stimulus

official-uvm-core