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aragor-s-celestial-quest

LaTeX source files for my book "Aragor's Celestial Quest."

branch-coverage

BIL481 Assignment 2

buildexecutable.jl

Build a standalone executables from a Julia script

circt

Circuit IR Compilers and Tools

city

2016-2017 Spring BIL 214 Homework 3

clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

d3d11-engine

D3D11 Experimental an old project imported from Bitbucket

dataflow-architecture

dnd-characters

An initial repository of D&D 3.5e characters

dumb-jose

Insecure library for an insecure format. GitHub mirror from https://gitea.treehouse.systems/jmercan/dumb-jose.

embench-iot

The main Embench repository

espresso

etu-coursebase

etu-coursebase

etu-tvl

Interpreter implementation for a three-valued logic language

euro2016

2015-2016 Summer BIL 143 Homework 4

gem5

The official repository for the gem5 computer-system architecture simulator.

hdw-store

2015-2016 Summer BIL 143 Final Project

lang-project

Experimental

lua-astronomical-almanac

Lua bindings for Astronomical Almanac (AA) a.k.a Moshier Ephemeris.

mimalloc

mimalloc is a compact general purpose allocator with excellent performance.

nandgame-sv

Experimental

newton-raphson

2017-2018 Spring BIL 211 Homework 1

null-ls.nvim

Use Neovim as a language server to inject LSP diagnostics, code actions, and more via Lua.

process-queue

2018-2019 Fall BIL 212 HW3

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

riscv-arch-test

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-opcodes

RISC-V Opcodes

riscv32-cosim-model

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

riscv32-decoder

A RISC-V instruction decoding library supporting 32-bit Integer (I), Multiply/Divide (M), Compressed (C), and Control and Status Register (Zicsr) instruction set extensions.