Comments (2)
There are a couple things here. At the moment the vec2 constructor that takes a vec4 is documented to return is_NaN when given a vector with undefined values. The issue is that the routine that copies the bits does not actually do this. This may be what we want and the constructor documentation needs to be changed and then in the vvp_arith_pow::recv_vec4() code the checks for undefined bits can use common code like what is done for a signed power (e.g. move the signed undefined check code outside of the if statement). Someone needs to spend some time checking which is the correct fix (change the constructor or change the power routine).
from iverilog.
I've just pushed a fix for this bug to the git master branch.
Note to the Icarus developers: I've changed the vvp_vector2_t constructor that takes a vvp_vector4_t value to take an optional second parameter that selects whether NaN or standard Verilog (XZ -> 0) semantics are used, as both behaviours are needed. I've made the default be standard Verilog semantics, otherwise there is a nasty gotcha where
vvp_vector2_t bit2 = bit4;
and
vvp_vector2_t bit2;
bit2 = bit4;
give different behaviour.
from iverilog.
Related Issues (20)
- Possible Data Transfer Anomaly HOT 8
- Nested generate statement not reported as syntax error
- ivl: logic_lpm.c:463: emit_nexus_port_signal: Assertion `! sig' failed.
- ivl: logic_lpm.c:485: find_local_signal: Assertion `! sig' failed. HOT 4
- Delayed transmission from tranif0/tranif1 primitives HOT 3
- Arrays can't be used in sensitivity lists HOT 6
- Clock of register is out of sync between RTL vs Yosys genereted netlist HOT 2
- data_out in rtl outputs at same clock cycle as data_out_reg (Flip-Flop issue) HOT 3
- Possible infinite loop in output evaluation HOT 2
- Request: add `exit` alias to `vvp`'s terminal interface HOT 2
- Please tag an official `v13.0.1`, or `v13.0.1-rc1`, or something HOT 6
- Executing multiple `vvp` instances of different files in parallel on the same computer causes vvp to hang HOT 3
- This code stalls instead of erroring HOT 2
- The simulation of iverilog and other tools is inconsistent HOT 1
- Adding signal output will cause abnormal simulation output in iverilog HOT 3
- Bug: assert: elab_expr.cc:2673: failed assertion base_index.size()+1 == net->packed_dimensions() HOT 3
- Changing Fixed VVP Path for Prebuilt Icarus Verilog on a Restricted System HOT 3
- Downgrade non-existing parameter to a warning (again) HOT 1
- Non-interactive mode of vvp (-n, -N) seems to be broken HOT 3
- Uninformative "syntax error" message when an undefined package name is used HOT 4
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