James E. Stine's Projects
Open-source repository for a standard-cell library characterizer using complete open-source tools
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
Oklahoma State University ECEN 2233 Digital Logic Design Fall 2024
Spring 2023 ecen4243 Computer Architecture Lab Material
Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University
Digital standard cells for GF180MCU provided by Oklahoma State University.
High-Speed Computer Arithmetic Spring 2024 at Oklahoma State University
This is a test
OSU Datapath/Control RV32 Single-Cycle and Pipelined Architecture in SV
Prefix adder generators for Verilog
Create C code to generate a bunch of random hex digits for use with SPICE decks
RISC-V Instruction Set Manual
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Files associated with IEEE SOCC 2018 publication
These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"
Submission template for Tiny Tapeout 04
Submission template for Tiny Tapeout 05
Submission template for Tiny Tapeout 8 - Verilog HDL Projects
Verilog Ethernet components for FPGA implementation
This is chiplogo a logo generator for VLSI chips.