Comments (1)
fixed 👍
from neorv32.
Related Issues (20)
- Rework bus system and memory map HOT 2
- Multi-driven Pin Vivado Error: what causes it and how to solve it? HOT 12
- Failed uploading binary executable image via UART HOT 16
- NEORV32 Multicore processor TMR implementation HOT 22
- ISA Zfinx extension HOT 8
- JTAG Scan chain interrogation failed: all ones HOT 14
- Wishbone burst access HOT 8
- `make check` passes but `make bin` fails with pre-built toolchain HOT 4
- Provide a neorv32_uart_vprintf function HOT 5
- Application binary does not persist in FPGA HOT 10
- Implementation with nextpnr-xilinx + prjxray doesn't work. HOT 5
- Clarification on Zfinx behavior for subnormal operands and results needed HOT 15
- Configure Bootloader.c booting from address other than start of IMEM (Ex: 0x2000, etc) HOT 2
- Processor doesn't park itself in a know good state prior to going to sleep HOT 3
- Nexys 4 DDR FPGA board flashing zephyr RTOS hello_world no output on default UART HOT 11
- Atomic accesses documentation error HOT 2
- neorv32_fifo vivado implementation issue HOT 1
- Implementation problem in XILINX ISE HOT 2
- Illegal instruction in coremark HOT 5
- Utilizing on-board SRAM HOT 16
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