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stnolting avatar stnolting commented on May 18, 2024

What synthesis tool you using? Lattice Radiant or an open-source setup?

Did you add the new neorv32_dma.vhd file to your setup? And did also add this file to the neorv32 library?

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biosbob avatar biosbob commented on May 18, 2024

i'm using same yosys/ghdl build flow as supported within the neorv32-setups/osflow folder....

my setup uses the neorv32/rtl/core/neorv32_top.vhd file, which itself has been updated in the latest commits to this repo....

as a further experiment, i first set IO_DMA_EN => in one of the neorv32/rtl/processor_template files and then tried building one of the configurations in neorv32-setups/osflow.... same problem....

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stnolting avatar stnolting commented on May 18, 2024

Oh, I think I have not updated the file list yet (-> https://github.com/stnolting/neorv32-setups/blob/main/osflow/filesets.mk) 🙈 I'll fix that ASAP!

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biosbob avatar biosbob commented on May 18, 2024

that explains it.... i can certainly make a quick change on my end, so i can proceed....

interesting, but i did NOT have a problem when using vivado to synthesize for the arty FPGA.... why??? because the create_project.tcl script "globs" all the neorv32/rtl/*.vhd files....

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stnolting avatar stnolting commented on May 18, 2024

neorv32-setup should be up-to-date now.

interesting, but i did NOT have a problem when using vivado to synthesize for the arty FPGA.... why??? because the create_project.tcl script "globs" all the neorv32/rtl/*.vhd files....

Yeah, that might be the reason. 😉

Does your setup work now?

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stnolting avatar stnolting commented on May 18, 2024

I think this can be closed, right?

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biosbob avatar biosbob commented on May 18, 2024

yes

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